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ht83xxx q-voice tm selection table body ht83004 HT83007 ht83010 ht83020 ht83038 ht83050 ht83074 voice rom size 64k-bit 128k-bit 192k-bit 384k-bit 768k-bit 1024k-bit 1536k-bit voice length 3 sec 6 sec 9 sec 18 sec 36 sec 48 sec 72 sec rev. 1.60 1 november 19, 2008 features operating voltage: 2.4v~5.2v up to 1 s (0.5 s) instruction cycle with 4mhz (8mhz) system clock system clock: 4mhz~8mhz (2.4v) crystal or rc oscillator for system clock 12 i/o pins 2k 15 program rom 80 8 ram two 8-bit programmable timer counter with 8-stage prescaler and one time base counter watchdog timer 4-level subroutine nesting halt function and wake-up feature reduce power consumption pwm circuit direct drive speaker or output by transistor 20-pin ssop (150mil/209mil) package 28-pin sop (300mil) package applications intelligent educational leisure products alert and warning systems sound effect generators general description the ht83xxx is 8-bit high performance microcontroller with voice synthesizer and tone generator. the ht83xxx is designed for applications on multiple i/os with sound effects, such as voice and melody. it can pro - vide various sampling rates and beats, tone levels, tem - pos for speech synthesizer and melody generator. the ht83xxx is excellent for versatile voice and sound effect product applications. the efficient mcu instruc- tions allow users to program the powerful custom appli- cations. the system frequency of ht83xxx can be up to 8mhz under 2.4v and include a halt function to re - duce power consumption. technical document tools information faqs application note
block diagram pin assignment ht83xxx rev. 1.60 2 november 19, 2008

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pad assignment ht83004/HT83007/ht83010 chip size: 2280 1475 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht83020/ht83038 chip size: 2180 1720 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht83xxx rev. 1.60 3 november 19, 2008 * + - 1 2 5 ' 6 * + * * 6 ' 5 2 1 - 7 8 9 * + - 1 2 5 . + . * . . / * / * 7 8 9 * + - 1 2 5 ' 6 * + * * 6 ' 5 2 1 - * + - 1 2 5 . + . * . . / * / *
ht83050/ht83074 chip size: 2180 2075 ( m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. pad coordinates ht83004/HT83007/ht83010 pad no. x y pad no. x y 1 940.400 307.150 12 654.200 587.900 2 940.400 212.150 13 551.200 587.900 3 940.400 109.150 14 940.400 571.200 4 940.400 14.150 15 940.400 476.200 5 940.400 88.850 16 940.600 368.500 6 940.400 183.850 17 940.600 273.000 7 940.400 286.850 18 896.250 165.350 8 940.400 381.850 19 904.900 63.250 9 947.200 587.900 20 904.900 56.300 10 852.200 587.900 21 904.900 266.800 11 749.200 587.900 ht83020/ht83038 pad no. x y pad no. x y 1 940.400 184.650 12 654.200 710.400 2 940.400 89.650 13 551.200 710.400 3 940.400 13.350 14 940.400 693.700 4 940.400 108.350 15 940.400 598.700 5 940.400 211.350 16 940.600 491.000 6 940.400 306.350 17 940.600 395.500 7 940.400 409.350 18 896.250 285.750 8 940.400 504.350 19 904.900 185.750 9 947.200 710.400 20 904.900 66.200 10 852.200 710.400 21 904.900 144.300 11 749.200 710.400 ht83xxx rev. 1.60 4 november 19, 2008 7 8 9 * + - 1 2 5 ' * + - 1 2 5 . + . * . . / * / * 6 * + * * 6 ' 5 2 1 -
ht83050/ht83074 pad no. x y pad no. x y 1 940.400 7.150 12 654.200 887.900 2 940.400 87.850 13 551.200 887.900 3 940.400 190.850 14 940.400 871.200 4 940.400 285.850 15 940.400 776.200 5 940.400 388.850 16 940.600 668.500 6 940.400 483.850 17 940.600 573.000 7 940.400 586.850 18 896.250 463.250 8 940.400 681.850 19 904.900 363.250 9 947.200 887.900 20 904.900 243.700 10 852.200 887.900 21 904.900 33.200 11 749.200 887.900 pad description pad name i/o mask option description pa0~pa7 i/o wake-up, pull-high or none bidirectional 8-bit i/o port. each bit can be configured as a wake-up input by mask option. software instructions determine the cmos output or schmitt trig - ger input with or without pull-high resistor (mask option). pb0~pb3 i/o pull-high or none bidirectional 4-bit i/o port. software instructions determine the cmos output or schmitt trigger input (pull-high resistor depending on mask option). vss negative power supply, ground vssp pwm negative power supply, ground vdd positive power supply vddp pwm positive power supply, ground res i schmitt trigger reset input, active low osc1, osc2 rc or crystal osc1 and osc2 are connected to an rc network or crystal (by mask option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. the system clock may came form the crystal, the two pins cannot be floating. pwm1, pwm2 o pwm output for driving a external transistor or speaker absolute maximum ratings supply voltage ..........................v ss +2.4v to v ss +5.5v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0 . 3v to v dd +0.3v operating temperature .......................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht83xxx rev. 1.60 5 november 19, 2008
d.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz/8mhz 2.4 5.2 v i stb1 standby current (watchdog off) 3v no load, system halt 1 a 5v 2 a i stb2 standby current (watchdog on) 3v no load, system halt 7 a 5v 10 a i dd operating current 3v no load, f sys =4mhz 3ma 5v 7ma i ol1 i/o port sink current 3v v ol =0.1v dd 7 ma 5v 15 ma i oh1 i/o port source current 3v v oh =0.9v dd 3.5 ma 5v 8 ma i ol2 pwm1/pwm2 sink current 3v v ol =0.1v dd 50 ma 5v 80 ma i oh2 pwm1/pwm2 source current 3v v oh =0.9v dd 14.5 ma 5v 26 ma v il1 input low voltage for i/o ports 3v 1 v 5v 2 v v ih1 input high voltage for i/o ports 3v 2 v 5v 3.2 v v il2 reset low voltage (res ) 3v 1.5 v 5v 2.5 v v ih2 reset high voltage (res ) 3v 2.1 v 5v 3.5 v f sys system frequency 3v r typical =275k 4.0 mhz r typical =144k 8.0 mhz r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k ht83xxx rev. 1.60 6 november 19, 2008
a.c. characteristics symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (rc osc) 2.4v~5.2v 4 8 mhz f sys2 system clock (crystal osc) 2.4v~5.2v 4 8 mhz f timer timer input frequency 2.4v~5.2v 0 8 mhz t wdtosc watchdog oscillator period 3v 50 100 200 s 5v 37 74 148 s t wdt1 watchdog time-out period (wdt osc) 3v without wdt prescaler 12 23 46 ms 5v 8 17 33 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s t drt data rom access timer 5 ms t drr data rom enable read read after data rom enable 30 ms characteristics curves r vs. f characteristics curve ht83xxx rev. 1.60 7 november 19, 2008 % 7 : 9 ; < % 7 = > 9 - - ' ' * 5 1 1 2 + - ? 1 ' 2 - *
v vs. f characteristics curve ht83xxx rev. 1.60 8 november 19, 2008 % 7 9 ; < % 7 - = > 9 % 7 9 ; < % 7 = > 9 ' 2 - * * ? 1 * ? 5 + ? + ? 1 - ? 1 ? * 1 ? 1 - ? 1 * - 2 ' * ? 1 * ? 5 + ? + ? 1 - ? - ? 1 1 ? * 1 ? 1 ' = > , - - : 2 = > , ' ' : - = > , * 5 1 : ' = > , + 6 : 2 = > , ' - : - = > , * 5 - :
ht83xxx rev. 1.60 9 november 19, 2008 mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 time base overflow 00000000100 timer counter 0 overflow 00000001000 timer counter 1 overflow 00000001100 skip program counter+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits * + - * + - * + - ;
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% 0 : execution flow functional description execution flow the system clock for the ht83xxx is derived from ei - ther a crystal or rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle con - sists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 11-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt or return from subroutine, the pc manipulates the program transfer by loading the ad - dress corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is ob - tained. the lower byte of the program counter (pcl) is a read/write register (06h). moving data into the pcl per - forms a short jump. the destination must be within 256 locations. when a control transfer takes place, an additional dummy cycle is required.
ht83xxx rev. 1.60 10 november 19, 2008 program memory rom the program memory stores the program instructions that are to be executed. it also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. the program memory size for ht83xxx is 2048 15 bits. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. the program always begins execution at location 000h each time the system is reset. location 004h this area is reserved for the time base interrupt ser - vice program. if the etbi (intc.1) is activated, and the interrupt is enabled and the stack is not full, the pro - gram will jump to location 004h and begins execution. location 008h this area is reserved for the 8-bit timer counter 0 in - terrupt service program. if a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008h and begins execution. location 00ch this area is reserved for the 8-bit timer counter 1 in - terrupt service program. if a timer interrupt results from a timer counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00ch and begins execution. table location any location in the rom space can be used as look up tables. the instructions tabrdc [m] (used for any bank) and tabrdl [m] (only used for last page of pro - gram rom) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined. the higher-order bytes of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register, which indicates the table location. stack register stack the stack register is a special part of the memory used to save the contents of the program counter. this stack is organized into four levels. it is neither part of the data nor part of the program space, and cannot be read or written to. its activated level is indexed by a stack pointer (sp) and cannot be read or written to. at a sub - routine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. the program counter is restored to its previous value from the stack at the end of subroutine or interrupt rou - tine, which is signaled by return instruction (ret or reti). after a chip resets, sp will point to the top of the stack. the interrupt request flag will be recorded but the ac- knowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. after the stack pointer is decremented (by ret or reti), the interrupt request will be serviced. this feature prevents stack overflow and allows programmers to use the structure more easily. in a similar case, if the stack is full and a call is subsequently executed, stack overflow oc - curs and the first entry is lost. instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: current program rom table @7~@0: write @7~@0 to tblp pointer register p10~p8: bits of current program counter = - = ' = =
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ht83xxx rev. 1.60 11 november 19, 2008 data memory ram the data memory is designed with 80 8 bits. the data memory is further divided into two functional groups, namely, special function registers (00h~2ah) and general purpose user data memory (30h~7fh). although most of them can be read or be written to, some are read only. the general purpose data memory, addressed from 30h~7fh, is used for data and control information un - der instruction commands. the areas in the ram can directly handle the arithmetic, logic, increment, decrement and rotate operations. ex - cept some dedicated bits, each bit in the ram can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through the memory pointer register 0 (mp0:01h). indirect addressing register location 00h is indirect addressing registers that are not physically implemented. any read/write operation of [00h] accesses the ram pointed to by mp0 (01h) re - spectively. reading location 00h indirectly returns the re - sult 00h. while, writing it indirectly leads to no operation. accumulator acc (05h) the accumulator (acc) is related to the alu opera - tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc) status register status (0ah) this 8-bit status register (0ah) consists of a zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), watchdog time-out flag (to). it also records the status information and controls the operation sequence. except the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those in - tended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruc - tion. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati - cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. 3 0 % 3
% - = 1 = 2 = 5 = ' = 6 = = . = = = = ; = = = * = + = - = 1 = 2 = 5 = ' = 6 = = . = = = = ; = = = * = + = * = * = * * = * + = * - = * 1 = + = 5 ; = * 2 = * 5 = * ' = * 6 = * = * . = * ; = b % 8 % % % % c c ! . ! . ! = / ! = = ! = ! = ! / = ! = 0 % 3 %
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ht83xxx rev. 1.60 12 november 19, 2008 address ram mapping read/write description 00h iar0 r/w indirect addressing register 0 01h mp0 r/w memory pointer 0 05h acc r/w accumulator 06h pcl r/w program counter lower-order byte address 07h tblp r/w table pointer lower-order byte register 08h tblh r table higher-order byte content register 09h wdts r/w watchdog timer option setting register 0ah status r/w status register 0bh intc r/w interrupt control register 0 0dh tmr0 r/w timer counter 0 register 0eh tmr0c r/w timer counter 0 control register 10h tmr1 r/w timer counter 1 register 11h tmr1c r/w timer counter 1 control register 12h pa r/w port a i/o data register 13h pac r/w port a i/o control register 14h pb r/w port b i/o data register 15h pbc r/w port b i/o control register 18h latch0h r/w voice rom address latch 0 [a17, a16] 19h latch0m r/w voice rom address latch 0 [a15~a8] 1ah latch0l r/w voice rom address latch 0 [a7~a0] 26h pwmcr r/w pwm control register 27h pwml r/w, higher-nibble available only pwm output data p3~p0 to pwml7~pwml4 28h pwmh r/w pwm output data p11~p4 to pwmh7~pwmh0 29h vol r/w, higher-nibble available only volume control register and volume controlled by vol8~vol4 2ah latchd r voice rom data register 2bh~2fh unused 30h~7fh user data ram r/w user data ram note: r: read only w: write only r/w: read/write interrupts the ht83xxx provides two 8-bit programmable timer interrupts, and a time base interrupt. the interrupt con - trol registers (intc:0bh) contain the interrupt control bits to set to enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in - terrupt needs servicing within the service routine, the emi bit and the corresponding intc bit may be set to al - low interrupt nesting. if the stack is full, the interrupt re - quest will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. only the program counter is pushed onto the stack. the programmer must save the contents of the register or status register (status) in advance if they are altered by an interrupt service pro - gram which corrupts the desired control sequence.
ht83xxx rev. 1.60 13 november 19, 2008 bit no. label function 0 c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1 ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. 3 ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5 to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register the internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt request flag (t0f:bit 5 of intc), caused by a timer counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the internal timer counter 1 interrupt is initialized by setting the timer counter 1 interrupt request flag (t1f:bit 6 of intc), caused by a timer counter 1 overflow. when the interrupt is enabled, and the stack is not full and the t1f bit is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. time base interrupt is triggered by set intc.1 (etbi) which sets the related interrupt request flag (tbf:bit 4 of intc). when the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (tbf) and emi bits will be cleared to disable other interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgment are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, the ret or reti instruction may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. the timer counter 0/1 interrupt request flag (t0f/t1f) which enables timer counter 0/1 control bit (et0i/ et1i), the time base interrupt request flag (tbf) which enables time base control bit (etbi) from the interrupt control reg - ister (intc:0bh) emi, etbi, et0i, et1i are used to con - trol the enabling/disabling of interrupts. these bits prevent the requested interrupt begin serviced. once the interrupt request flags (t0f, t1f, tbf) are set, they will remain in the intc register until the interrupts are ser- viced or cleared by a software instruction. it is recommended that application programs do not use call subroutines within an interrupt subroutine. inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt enable is not well con- trolled, once a call subroutine if used in the interrupt subroutine will corrupt the original control sequence. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 etbi controls the time base interrupt (1= enabled; 0= disabled) 2 et0i controls the timer 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer 1 interrupt (1= enabled; 0= disabled) 4 tbf time base interrupt request flag (1= active; 0= inactive) 5 t0f timer 0 request flag (1= active; 0= inactive) 6 t1f timer 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc (0bh) register
ht83xxx rev. 1.60 14 november 19, 2008 ws7 ws6 ws5 ws4 ws3 ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register interrupt source priority vector time base interrupt 1 04h timer counter 0 overflow 2 08h timer counter 1 overflow 3 0ch oscillator configuration the ht83xxx provides two oscillator circuits for system clock, i.e., rc oscillator and crystal oscillator. no matter what type of oscillator.. the signal is used for the system clock. the halt mode stops the system oscillator to conserve power. if the rc oscillator is used, an external resistor between osc1 and vss is required, and the range of the resistance should be from 144k to 275k . the system clock, divided by 4. the rc oscillator pro - vides the most cost effective solution. however, the fre - quency of the oscillation may vary with vdd, temperature, and the chip itself due to process varia - tions. it is therefore not suitable for timing sensitive op - erations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex- ternal capacitors in osc1 and osc2 are required. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), decided by mask options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpre - dictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with pe - riod 78 s normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approxi - mately 20ms. this time-out period may vary with tem - perature, vdd and process variations. by invoking the wdt prescaler, longer time-out period can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of wdts(09h)) can give different time-out period. if ws2, ws1, ws0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize a chip reset and set the status bit to . whereas in the halt mode, the overflow will initialize a warm re - set only the program counter and sp are reset to zero. to clear the contents of the wdt (including the wdt prescaler), three methods are adopted; external reset (external reset (a low level to res ), software instruc- tions, or a halt instruction. the software instruction is clr wdt and execution of the clr wdt instruc- tion will clear the wdt.
0 % 0 0
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* * # $ , - system oscillator
ht83xxx rev. 1.60 15 november 19, 2008 power down halt the halt mode is initialized by a halt instruction and results in the following: the system oscillator will be turned off but the wdt oscillator keeps running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and recount again. all i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per- forms a warm reset . by examining the to and pdf flags, the reason for the chip reset can be determined. the pdf flag is cleared when the system powers-up or executes the clr wdt instruction, and is set when the halt instruction is executed. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer. the other maintain their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. if awakening from an interrupt, two se - quence may occur. if the related interrupt is disabled or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. if the inter - rupt is enabled and the stack is not full, the regular inter - rupt response takes place. once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. in other words, a dummy cycle period will be inserted after a wake-up. if the wake-up results from an interrupt ac - knowledge, the actual interrupt subroutine will be de - layed by one more cycle. if the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be dis - abled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are 3 ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during any other reset conditions. most registers are reset to their initial condi - tion when the reset conditions are met. by examining the pdf flag and to flag, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged
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reset timing chart reset circuit
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ht83xxx rev. 1.60 16 november 19, 2008 to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a halt state. when a system power up occurs, the sst delay is added during the reset period. but when the reset co - mes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer counter off input/output ports input mode stack pointer points to the top of the stack timer counter 0/1 the tmr0/tmr1 is internal clock source only, i.e. (tm1, tm0) = (0, 1). there is a 3-bit prescaler (tmrs2, tmrs1, tmrs0) which defines different division ratio of tmr0/tmr1 s clock source. bit no. label function 0~2 tmrs2, tmrs1, tmrs0 defines the operating clock source (tmrs2, tmrs1, tmrs0) 000: clock source/2 001: clock source/4 010: clock source/8 011: clock source/16 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 3 te defines the tmr0/tmr1 active edge of timer counter 4 ton enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 tm0, tm1 defines the operating mode (tm1, tm0) tmr0c (0eh)/tmr1c (11h) register note: tmr0c/tmr1c bit 3 always write 0 tmr0c/tmr1c bit 5 always write 0 tmr0c/tmr1c bit 6 always write 1 tmr0c/tmr1c bit 7 always write 0
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ht83xxx rev. 1.60 17 november 19, 2008 the tmr0c is the timer counter 0 control register, which defines the timer counter 0 options. the timer counter 1 has the same options as the timer counter 0 and is defined by tmr1c. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c/tmr1c) should be set to 1 . the overflow of the timer counter is one of the wake-up sources. no matter what the operation mode is, writing a 0 to et0i/et1i can disable the corresponding interrupt service. the tmr0/1 is internal clock source only. there is a 3-bit prescaler (tmrs2, tmrs1, tmrs0) which de - fines different division ratio of tmr0/1 s clock source. time base the time base enables the counting operation by intc.1 (etbi) bit. the overflow to interrupt as set intc.4. the time base is internal clock source only. time base of 1ms to overflow as system clock is 4mhz. time base of 0.5ms to overflow as system clock is 8mhz. the registers states are summarized in the following table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr0c xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx tmr1c xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pbc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu latch0h ---- --xx ---- --uu ---- --uu ---- --uu ---- --uu latch0m xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu latch0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pwmcr 0--- 00-0 u--- uu-u u--- uu-u u--- uu-u u--- uu-u pwml xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- pwmh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol xxxx ---- uuuu ---- uuuu ---- uuuu ---- uuuu ---- latchd xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu note: u means unchanged x means unknown means undefined * -
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ht83xxx rev. 1.60 18 november 19, 2008 input/output ports there are 12 bidirectional input/output lines in the microcontroller, labeled from pa to pb, which are mapped to the data memory of [12h], [14h] respec - tively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a, [m] (m=12h, 14h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an in - put, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13hm 15h. after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h) in - structions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the wake-up capability of port a is determined by mask option. there is a pull-high option available for all i/o lines. once the pull-high option is selected, all i/o lines have pull-high resistors. otherwise, the pull-high resistors are absent. it should be noted that a non-pull-high i/o line operating in input mode will cause a floating state. f & f f & f
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ht83xxx rev. 1.60 19 november 19, 2008 pulse width modulation output pwml/pwmh (27h/28h) the ht83xxx provide one 12-bit pwm interface for driving an external 8 speaker. the programmer must write the voice data to register pwml/pwmh (27h/28h) pulse width modulation control register pwmcr (26h) bit 7 bit 6 bit 5 bit 4 bit 3 (r/w) bit 2 (r/w) bit 1 bit 0 (r/w) msb_sign single_pwm vromc pwmc
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% . pwm pwmc: start bit of pwm output pwm start counter: 0 to 1 pwm stop counter: 1 to 0 after waiting one cycle end , stop the pwm counter and keep in low signal vromc: enable voice rom power circuit (1=enable; 0=disable) single_pwm: driving pwm signal by pwm1 output. (1=pwm1 output; 0=pwm1/pwm2 output) the ht83xxx provide an 12-bit (bit 7 is a sign bit, if sin - gle_pwm = 0) pwm interface. the pwm provides two pad outputs: pwm1, pwm2 which can directly drive a piezo or an 8 speaker without adding any external ele - ment (green mode), or using only port pwm1 (set sin - gle_pwm = 1) to drive piezo or an 8 speaker with external element. when setting single_pwm= 1, choose voice data7~ data1 as the output data (no sign bit on it). if the sign bit is 0, then the signal is output to pwm1and the pwm2 will get a gnd level voltage after setting start bit to 1. if the sign bit is 1, then the signal is output to pwm2 and the pwm1 will get a gnd level voltage after setting start bit to 1. pwm output initial low level , and stop in low level if pwmc from low to high then start pwm output latch new data , if no update then keep the old value. if pwmc from high to low, in duty end, stop pwm output and stop the counter. voice rom data address latch counter the voice rom data address latch counter is the hand - shaking between the microcontroller and voice rom, where the voice codes are stored. one 8-bit of voice rom data will be addressed by setting 18-bit address latch counter latch0h/latch0m/latch0l. after the 8-bit voice rom data is addressed, a few instruction cy - cles (4 s at least) will be generated to latch the voice rom data, then the microcontroller can read the voice data from latchd (2ah). example: read an 8-bit voice rom data which is lo - cated at address 000007h by address latch 0 set [26h].2 ; enable voice rom circuit mov a, 07h ; mov latch0l, a ; set latch0l to 07h mov a, 00h ; mov latch0m, a ; set latch0m to 00h mov a, 00h ; mov latch0h, a ; set latch0h to 00h call delay time ; delay a short period of time mov a, latchd ; get voice data at 000007h
application circuits single pwm mode ht83xxx rev. 1.60 20 november 19, 2008 mask option mask option description pa wake-up enable or disable pa wake-up function watchdog timer (wdt) enable or disable wdt function wdt clock source is from wdtosc or t1 pa pull-high enable or disable pa pull-high pb pull-high enable or disable pb pull-high osc option crystal or resistor type f osc r typical table (v dd =3v) f osc r typical 4mhz
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ht83xxx rev. 1.60 21 november 19, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc - tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht83xxx rev. 1.60 22 november 19, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht83xxx rev. 1.60 23 november 19, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht83xxx rev. 1.60 24 november 19, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht83xxx rev. 1.60 25 november 19, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht83xxx rev. 1.60 26 november 19, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht83xxx rev. 1.60 27 november 19, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht83xxx rev. 1.60 28 november 19, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht83xxx rev. 1.60 29 november 19, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht83xxx rev. 1.60 30 november 19, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht83xxx rev. 1.60 31 november 19, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht83xxx rev. 1.60 32 november 19, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht83xxx rev. 1.60 33 november 19, 2008
package information 20-pin ssop (150mil) outline dimensions symbol dimensions in mil min. nom. max. a 228 244 b 150 158 c8 12 c 335 347 d49 65 e 25 f4 10 g15 50 h7 10 0 8 ht83xxx rev. 1.60 34 november 19, 2008 * . ; g =
20-pin ssop (209mil) outline dimensions symbol dimensions in mil min. nom. max. a 291 323 b 196 220 c9 15 c 271 295 d65 73 e 25.59 f4 10 g26 34 h4 8 0 8 ht83xxx rev. 1.60 35 november 19, 2008 * . ; g =
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c 697 713 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht83xxx rev. 1.60 36 november 19, 2008 * ' 1 - . ; g =
product tape and reel specifications reel dimensions ssop 20s (150mil), ssop 20n (209mil) symbol description dimensions in mm a reel outer diameter 330.0
1.0 b reel inner diameter 100.0
1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0
0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2
0.2 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.0
1.0 b reel inner diameter 100.0
1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0
0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2
0.2 ht83xxx rev. 1.60 37 november 19, 2008 . *
carrier tape dimensions ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0
0.1 e perforation position 1.75
0.10 f cavity to perforation (width direction) 7.5
0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 6.5
0.1 b0 cavity width 9.0
0.1 k0 cavity depth 2.3
0.1 t carrier tape thickness 0.30
0.05 c cover tape width 13.3
0.1 ht83xxx rev. 1.60 38 november 19, 2008 / ;
& . % 3 : % 3 % % %
" % 0 % " 0 % 0
% %
" % % ? 0 % = 0
ssop 20n (209mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 12.0
0.1 e perforation position 1.75
0.10 f cavity to perforation (width direction) 7.5
0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 7.1
0.1 b0 cavity width 7.2
0.1 k0 cavity depth 2.0
0.1 t carrier tape thickness 0.30
0.05 c cover tape width 13.3
0.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0
0.3 p cavity pitch 12.0
0.1 e perforation position 1.75
0.10 f cavity to perforation (width direction) 11.5
0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 10.85
0.10 b0 cavity width 18.34
0.10 k0 cavity depth 2.97
0.10 t carrier tape thickness 0.35
0.01 c cover tape width 21.3
0.1 ht83xxx rev. 1.60 39 november 19, 2008
ht83xxx rev. 1.60 40 november 19, 2008 copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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